This invention relates to a memory circuit capable of operation in two word configurations. More particularly, the invention relates to the power-line interconnections of the memory circuit.
The term "word configuration" refers to the number of data bits output simultaneously. A typical memory of this type has a first mode in which only one data bit is output at a time, and a second mode in which four or eight data bits are output at once. The mode is generally selected by an option such as a wire bonding option when the memory circuit is manufactured. Specifically, the memory circuit comprises a semiconductor chip having a mode pad that can be optionally connected to a power-supply (Vcc) post. The memory circuit operates in one mode if the mode pad is connected to the Vcc post, and in the other mode if the mode pad is not connected to the Vcc post.
The Vcc post is also connected to a Vcc pad on the semiconductor chip, which feeds power to data output buffers and various other circuits on the semiconductor chip. These other circuits include circuits that receive input signals at the transistor-transistor logic (TTL) level.
A problem with this memory circuit is that since all the data output buffers are powered from the Vcc pad, in the second mode of operation considerable charge and discharge current may flow through this pad, particularly when multiple "1" data bits are output. Due to the impedance of the bonding wire connecting the Vcc pad to the Vcc post, a large potential drop occurs at the Vcc pad. This in turn may lead to malfunctioning of the peripheral circuits powered from the Vcc pad, particularly to the malfunctioning of TTL input circuits. This problem has been difficult to solve.